Power supply design is the single most underestimated discipline in Bluetooth module integration. A module with excellent RF sensitivity and a polished firmware stack can lose 6–10 dB of receiver range, experience random brown-out resets, or drain a coin cell in weeks rather than years if the power delivery network (PDN) is poorly designed. This article walks through the complete power supply design flow for BLE modules, covering topology selection, ripple budgeting, inrush current management, battery discharge matching, and measurement verification.
We use real-world parameters from Nordic nRF52840, Silicon Labs EFR32BG22, TI CC2640R2, and Espressif ESP32-C3 modules to illustrate the trade-offs. Every calculation is shown explicitly so you can substitute your own module’s datasheet values.
1. Why Power Supply Quality Directly Affects RF Performance
BLE radios are sensitive to supply noise because the PLL, VCO, and PA all share the same power rail (or coupled rails). The relationship between supply ripple and phase noise is approximately:
ΔL(dBc/Hz) ≈ 20 × log10(V_ripple / V_supply) + PSRR_PA
For a typical module running at 3.0 V with a PA power supply rejection ratio (PSRR) of −25 dB at 1 MHz offset, a 50 mV ripple produces:
ΔL ≈ 20 × log10(0.05 / 3.0) + (−25) = 20 × (−35.6) + (−25) = −35.6 − 25 = −60.6 dBc/Hz
This is right at the BLE specification limit of −62 dBc/Hz for adjacent channel rejection. Push ripple to 100 mV and the phase noise degrades to −54.6 dBc/Hz, failing compliance. The message is clear: supply ripple is not a secondary concern; it directly determines whether your module passes Bluetooth qualification.
2. Power Supply Topology Selection: LDO vs Buck vs Buck-Boost
Three topologies dominate BLE module designs. The choice depends on input voltage range, efficiency requirements, board area, and noise sensitivity.
| Parameter | LDO | Buck Converter | Buck-Boost |
|---|---|---|---|
| Efficiency | 35–70% (V_out/V_in) | 85–95% | 80–92% |
| Output Ripple | 5–50 μV (ultra-low) | 5–30 mV (switching) | 10–50 mV |
| Quiescent Current | 0.3–5 μA | 5–50 μA | 10–80 μA |
| Component Count | 1 (IC only) | 4–5 (IC + L + C × 2) | 5–6 (IC + L + C × 2 + extra) |
| Cost (BOM) | $0.03–0.15 | $0.20–0.60 | $0.30–0.80 |
| Board Area | 0.6–1.0 mm² | 4–8 mm² | 6–10 mm² |
| EMI | Negligible | Moderate (switching harmonics) | Moderate–High |
| Battery Life (CR2032, 1s interval) | 2.5–3.5 years | 3.0–4.0 years | 2.0–3.0 years |
Decision matrix:
- Battery = CR2032 (2.0–3.0 V) → LDO: The input voltage is always above or near the module’s 1.8–3.0 V range. A buck converter’s efficiency advantage disappears when V_in − V_out < 200 mV. LDO quiescent current is 10–100× lower, which matters far more for duty-cycled BLE tags.
- Battery = Li-ion (3.0–4.2 V) → Buck: The 1.2 V headroom between 4.2 V and 3.0 V wastes 28% of energy in an LDO. A buck converter at 90% efficiency saves this, extending battery life by ~25%.
- Battery = Alkaline 2× AA (2.0–3.2 V) → Buck-Boost: The voltage crosses the module’s V_out, requiring both step-down and step-up capability. A buck-boost maintains regulated 3.0 V across the full discharge curve.
- USB-powered or 5 V rail → Buck + LDO cascade: A buck converter steps 5 V → 3.3 V at 92% efficiency, followed by an LDO regulating 3.3 V → 3.0 V for the RF section. This gives both efficiency and low noise.
3. LDO Regulator Design: Dropout, Quiescent Current, and PSRR
When selecting an LDO for a BLE module, three parameters dominate: dropout voltage, quiescent current, and PSRR at the switching frequency of any upstream converter.
3.1 Dropout Voltage
Dropout voltage is the minimum V_in − V_out required for regulation. For a CR2032-powered module operating down to 2.0 V end-of-life, with a 3.0 V regulated rail:
V_dropout_max = V_battery_EOL − V_rail = 2.0 V − 1.8 V = 0.2 V
(assuming the module can tolerate 1.8 V on VDD). Most general-purpose LDOs have 200–500 mV dropout at 15 mA load, which is marginal. Ultra-low-dropout LDOs like the TI TPS7A02 or NCP171 achieve 35–80 mV at 10 mA, providing comfortable margin.
3.2 Quiescent Current
For a BLE tag that sleeps 99.9% of the time (1-second advertising interval, ~3 ms active), the LDO quiescent current dominates the average power budget:
I_avg = I_sleep × 0.999 + I_tx × 0.001 = I_q_ldo × 0.999 + 15 mA × 0.001
| LDO | I_q (nA) | 10-yr CR2032 drain from I_q (mAh) | % of 220 mAh cell |
|---|---|---|---|
| Tlps7A02 (TI) | 25 | 2.2 | 1.0% |
| NCP171 (onsemi) | 50 | 4.4 | 2.0% |
| AP2112 (Diodes) | 55,000 | 4,818 | exceeds cell |
| ME6211 (Microne) | 40,000 | 3,504 | exceeds cell |
The AP2112 and ME6211 are common low-cost LDOs, but their 40–55 μA quiescent current drains a CR2032 in under 2 months even with zero BLE activity. Always verify I_q against your battery capacity × design lifetime.
3.3 Power Supply Rejection Ratio (PSRR)
PSRR defines how much input ripple is attenuated at the output. When cascading a buck converter with an LDO, the total ripple at the module VDD is:
V_ripple_out = V_ripple_buck × 10^(−PSRR_ldo / 20)
For a buck converter with 20 mV ripple at 2.4 MHz (typical switching frequency), cascaded with an LDO having 45 dB PSRR at 2.4 MHz:
V_ripple_out = 0.020 × 10^(−45/20) = 0.020 × 0.00562 = 0.000112 V = 112 μV
This 112 μV is well below the 1 mV target for BLE modules. However, PSRR degrades at higher frequencies. At 10 MHz, the same LDO may only provide 20 dB PSRR, yielding 2 mV ripple. Always check the PSRR-vs-frequency curve in the LDO datasheet, not just the headline 1 kHz number.
4. Buck Converter Design: Efficiency, Switching Frequency, and Inductor Selection
For Li-ion or USB-powered BLE modules, a buck converter is the primary regulator. The design involves three key decisions: switching frequency, inductor value, and output capacitor selection.
4.1 Switching Frequency Trade-off
| Parameter | 1.5 MHz | 3.0 MHz | 6.0 MHz |
|---|---|---|---|
| Inductor value (for 30% ripple) | 4.7 μH | 2.2 μH | 1.0 μH |
| Inductor footprint | 2.0 × 2.5 mm | 1.5 × 1.5 mm | 1.0 × 0.5 mm |
| Light-load efficiency (1 mA) | 78% | 82% | 85% |
| Full-load efficiency (100 mA) | 88% | 90% | 87% |
| EMI harmonics in BLE band | Low (2nd harmonic at 3 MHz) | Moderate (harmonic near 2.4 GHz? No) | Higher order at 2.4 GHz unlikely but layout-critical |
| Quiescent current | 8–15 μA | 5–10 μA | 4–8 μA |
Higher switching frequencies allow smaller inductors and capacitors, reducing board area. However, switching losses increase with frequency, reducing full-load efficiency. For BLE modules, 3 MHz is the sweet spot: small inductor, good light-load efficiency (BLE is duty-cycled), and switching harmonics are far from the 2.4 GHz RF band.
4.2 Inductor Selection
The inductor value determines the ripple current, which in turn affects output voltage ripple and efficiency. The ripple current is:
ΔI_L = (V_in − V_out) × D / (f_sw × L)
where D = V_out / V_in is the duty cycle. For V_in = 4.0 V, V_out = 3.0 V, f_sw = 3 MHz, L = 2.2 μH:
D = 3.0 / 4.0 = 0.75
ΔI_L = (4.0 − 3.0) × 0.75 / (3×10⁶ × 2.2×10⁻⁶) = 0.75 / 6.6 = 0.114 A = 114 mA
This is a 114 mA peak-to-peak ripple around the average load current. For BLE TX at 15 mA, the inductor current swings from −42 mA to +72 mA. The negative swing means the converter enters DCM (Discontinuous Conduction Mode), which is normal for light loads and actually improves efficiency.
Key inductor parameters:
- DCR (DC resistance): < 100 mΩ for efficiency. A 150 mΩ DCR wastes I²×R = 0.015² × 0.15 = 34 μW at 15 mA — negligible, but at 200 mA it’s 6 mW.
- Saturation current: Must exceed the peak inductor current (I_avg + ΔI_L/2). For BLE modules, 500 mA rating is sufficient.
- Shielded construction: Unshielded drum-core inductors radiate magnetic fields that couple into the antenna. Always use shielded (metal or resin-encased) inductors for BLE designs.
4.3 Output Capacitor and Ripple
Output voltage ripple in a buck converter has two components: capacitive ripple and ESR ripple:
V_ripple = ΔI_L / (8 × f_sw × C_out) + ΔI_L × ESR
For C_out = 10 μF (MLCC, X5R), ESR = 5 mΩ, ΔI_L = 114 mA, f_sw = 3 MHz:
V_ripple_cap = 0.114 / (8 × 3×10⁶ × 10×10⁻⁶) = 0.114 / 240 = 0.475 mV
V_ripple_esr = 0.114 × 0.005 = 0.57 mV
V_ripple_total = 1.05 mV
Note that MLCC capacitance drops with DC bias. A 10 μF 6.3V X5R capacitor may lose 40% of its capacitance at 3.0 V DC bias, effectively becoming 6 μF. This increases ripple to 1.75 mV — still acceptable, but the margin shrinks. Always check the DC bias derating curve.
5. Ripple Budget Calculation for BLE RF Performance
A systematic ripple budget allocates allowable noise across the entire signal chain, from battery to RF PA. Here is a worked example for a CR2032-powered BLE tag:
| Stage | Noise Source | Magnitude | Attenuation | At Module VDD |
|---|---|---|---|---|
| Battery (CR2032) | Internal resistance transient | 80 mV (at 15 mA TX) | — | 80 mV |
| Decoupling cap (10 μF) | Low-pass filtering | — | −18 dB @ 1 MHz | 10.1 mV |
| LDO (PSRR 45 dB) | Regulation | — | −45 dB @ 1 MHz | 57 μV |
| Module internal decoupling | On-module caps | — | −12 dB @ 1 MHz | 14 μV |
| Final at PA | — | — | — | 14 μV |
The final 14 μV ripple at the PA translates to phase noise of:
ΔL = 20 × log10(14×10⁻⁶ / 3.0) + (−25) = 20 × (−106.6) + (−25) = −131.6 dBc/Hz
This is 69 dB below the BLE specification limit — excellent margin. The critical takeaway is that the battery internal resistance transient (80 mV) is attenuated by three stages. If any stage is bypassed (e.g., direct battery-to-module connection without decoupling), the ripple at the PA jumps to 80 mV, producing −64 dBc/Hz phase noise — failing compliance.
6. Inrush Current: Causes, Measurement, and Mitigation
Inrush current is the transient surge when power is first applied, caused by charging bulk capacitors and the startup of switching regulators. For BLE modules, inrush can reach 500 mA–2 A for 50–200 μs, which is problematic for:
- CR2032 batteries: Maximum recommended pulse current is 15 mA. Inrush above this causes voltage sag that can trigger brown-out resets.
- USB current limits: USB 2.0 specifies 100 mA (unconfigured) / 500 mA (configured). Inrush above 100 mA for >100 ms may trip host overcurrent protection.
- Battery protection ICs: Overcurrent protection typically triggers at 2–3 A for 10 ms. Repeated inrush events can fatigue the protection fuse.
6.1 Calculating Inrush Current
The inrush current into a capacitor charged through a resistance R is:
I_inrush = V / R × e^(−t/RC)
For a module with 47 μF total bulk capacitance, connected to a 3.0 V battery with 200 mΩ internal resistance:
I_peak = 3.0 / 0.2 = 15 A (theoretical, instantaneous)
In practice, PCB trace inductance (~5 nH) limits the slew rate, and the actual peak is 2–5 A with a time constant of RC = 0.2 × 47×10⁻⁶ = 9.4 μs. The total charge transferred is Q = C × V = 47 μF × 3.0 V = 141 μC, which is negligible for battery life but the instantaneous current can cause problems.
6.2 Inrush Mitigation Techniques
| Technique | Inrush Reduction | Complexity | Side Effects |
|---|---|---|---|
| Series resistor (10 Ω) | 300 mA → 27 mA | Low | 3.4 mW drop at 15 mA TX, wastes power |
| Soft-start LDO | Programmed ramp (0.5–5 ms) | Low | None (built into IC) |
| Load switch with slew control | Programmed dV/dt | Medium | Extra component ($0.05–0.15) |
| NTC thermistor | 10× reduction when cold | Low | Slow reset after power cycle, temperature-dependent |
| Staggered power-up | Sequential cap charging | High | Requires GPIO control of enable pins |
For CR2032-powered BLE tags, the best approach is a soft-start LDO with a 1–2 ms ramp time. The TPS7A02 has a factory-programmed 150 μs soft-start, which limits inrush to about 10 mA for a 47 μF load — safely within CR2032 limits. For USB-powered modules, a load switch with controlled slew rate (e.g., TPS22918 with 150 μs slew) is preferred because it provides programmable timing independent of the LDO.
7. Battery Discharge Curve Matching
The power supply must maintain regulation across the entire battery discharge curve. Each battery chemistry has a distinct voltage profile:
| Battery | V_fresh | V_nominal | V_EOL | Internal R (fresh → EOL) | Usable capacity |
|---|---|---|---|---|---|
| CR2032 (Li-MnO₂) | 3.3 V | 3.0 V | 2.0 V | 5 Ω → 25 Ω | 220 mAh |
| Li-ion (ICR18650) | 4.2 V | 3.7 V | 3.0 V | 50 mΩ → 150 mΩ | 2500 mAh |
| Alkaline AA (×2) | 3.2 V | 2.8 V | 1.8 V | 200 mΩ → 800 mΩ | 2500 mAh |
| NiMH AA (×2) | 2.8 V | 2.4 V | 2.0 V | 50 mΩ → 200 mΩ | 2000 mAh |
| Lisocl₂ (ER14505) | 3.7 V | 3.6 V | 2.8 V | 10 Ω → 50 Ω | 2400 mAh |
CR2032 internal resistance trap: The 25 Ω EOL internal resistance creates a 375 mV sag at 15 mA TX current. If the module’s brown-out detector (BOD) is set at 1.8 V, and the LDO dropout is 100 mV, the minimum battery voltage for reliable operation is:
V_batt_min = V_BOD + V_dropout + I_tx × R_internal = 1.8 + 0.1 + 0.015 × 25 = 1.8 + 0.1 + 0.375 = 2.275 V
This means 15% of the CR2032 capacity (between 2.0 V and 2.275 V) is unusable. Lowering the BOD threshold to 1.7 V (if the module supports it) reclaims this capacity, but risks flash write corruption at low voltages. The practical solution is to reduce TX power from +4 dBm to 0 dBm, cutting current from 15 mA to 7 mA and reducing sag to 175 mV, making V_batt_min = 1.975 V — nearly the full discharge curve.
8. Power Sequencing and Brown-Out Detection
BLE modules typically require multiple power rails: VDD (1.8–3.6 V for the SoC), VDD_PA (RF power amplifier, same as VDD on most modules), and VDD_FLASH (internal flash, often 1.8–3.6 V). Power sequencing errors can cause latch-up, flash corruption, or spurious resets.
8.1 Brown-Out Detector Configuration
The BOD monitors VDD and resets the MCU if it drops below a configurable threshold. For BLE modules, the BOD threshold should be set above the minimum flash write voltage:
| Module SoC | Min flash write V | Recommended BOD | BOD current |
|---|---|---|---|
| nRF52840 | 1.7 V | 1.8 V (BOD level 4) | 5 μA |
| EFR32BG22 | 1.8 V | 1.9 V (BOD level 5) | 3 μA |
| CC2640R2 | 1.8 V | 1.85 V (BOD level 3) | 2 μA |
| ESP32-C3 | 2.0 V | 2.1 V (BOD level 2) | 8 μA |
The BOD current adds to the sleep budget. On the nRF52840, the 5 μA BOD current is 16% of the total 30 μA sleep current. Some designs disable BOD during sleep and rely on the RTC wake-up to re-enable it, saving 5 μA at the cost of flash corruption risk if VDD sags during sleep.
8.2 Power-On Reset (POR) Timing
The POR circuit ensures the MCU starts only when VDD is stable. A typical POR sequence:
- VDD rises through POR threshold (typically 1.0–1.4 V)
- POR holds reset for 50–200 μs after VDD crosses threshold
- BOD checks VDD > BOD threshold
- If BOD passes, MCU starts boot sequence (bootloader, then application)
- Total time from power application to first instruction: 200–800 μs
If the supply ramps slowly (e.g., a buck converter with 5 ms soft-start), VDD may oscillate around the POR threshold, causing multiple reset cycles. The fix is to ensure the supply ramp time is shorter than the POR delay, or use an external reset IC with a precise threshold and fixed delay.
9. Decoupling Network Design
The decoupling network provides local charge storage to handle transient current demands from the BLE radio. A typical design uses three tiers:
| Tier | Capacitor | ESL/ESR | Effective Frequency | Purpose |
|---|---|---|---|---|
| Tier 1 (closest to pin) | 100 nF X7R 0402 | 0.4 nH / 20 mΩ | 10–500 MHz | TX/RX burst current |
| Tier 2 | 1 μF X5R 0603 | 0.6 nH / 10 mΩ | 1–10 MHz | LDO transient response |
| Tier 3 (bulk) | 10 μF X5R 0805 | 1.0 nH / 5 mΩ | 100 kHz–1 MHz | Battery sag compensation |
The key design rule: place Tier 1 within 2 mm of the VDD pin, connected via the shortest possible trace. At 2.4 GHz, 1 mm of trace adds ~0.6 nH of inductance, creating an impedance of Z = 2π × 2.4×10⁹ × 0.6×10⁻⁹ = 9 Ω — comparable to the capacitor’s impedance, halving its effectiveness.
For modules with separate VDD and VDD_PA pins, each pin needs its own Tier 1 capacitor. Do not share a single 100 nF between VDD and VDD_PA — the PA’s 15 mA transient will couple into the SoC’s digital rails, causing jitter on the crystal oscillator.
10. Thermal Considerations
Power dissipation in the regulator generates heat that affects module performance. For an LDO at 200 mA load with 1.2 V dropout:
P_diss = (V_in − V_out) × I_load = 1.2 × 0.2 = 0.24 W
The thermal resistance of a SOT-23-5 package is 200–300 °C/W, giving a temperature rise of 48–72 °C. This pushes the junction temperature to 70–95 °C in a 25 °C ambient — approaching the 125 °C maximum. The solution is either a larger package (SOT-89 at 150 °C/W) or a buck converter (0.04 W dissipation at 90% efficiency).
| Package | θ_JA (°C/W) | Max P_diss at 25 °C ambient | Max P_diss at 70 °C ambient |
|---|---|---|---|
| SOT-23-5 | 250 | 0.40 W | 0.22 W |
| SOT-89 | 150 | 0.67 W | 0.37 W |
| DFN-8 (2×2 mm) | 120 | 0.83 W | 0.46 W |
| WLCSP | 80 | 1.25 W | 0.69 W |
11. Vendor Module Power Architecture Comparison
| Module | SoC | VDD range | TX peak (0 dBm) | Sleep (system-off) | Internal DCDC | Recommended external reg |
|---|---|---|---|---|---|---|
| Raytac MDBT50Q | nRF52840 | 1.7–3.6 V | 4.6 mA | 0.4 μA | Yes (3 MHz buck) | LDO (CR2032) or direct VDD |
| SiLabs BGM220SC | EFR32BG22 | 1.8–3.8 V | 5.7 mA | 1.2 μA | Yes (3 MHz buck) | LDO (CR2032), DCDC bypass possible |
| TI CC2640R2F | CC2640R2F | 1.8–3.8 V | 6.1 mA | 1.0 μA | Optional (DCDC pin) | LDO or DCDC (Li-ion) |
| ESP32-C3-WROOM | ESP32-C3 | 3.0–3.6 V | 34 mA | 5 μA | Yes (internal LDO) | Buck (USB) or LDO (battery) |
The nRF52840 and EFR32BG22 have internal DC/DC converters that can be enabled in firmware, reducing TX current by 10–20%. However, the internal DCDC requires an external 2.2 μH inductor and 4.7 μF capacitor, which must be placed within 3 mm of the module’s DCDC pins. Skipping this external circuit and running in LDO mode costs 1–2 mA extra TX current — acceptable for USB-powered designs but significant for battery operation.
12. Power Supply Measurement and Verification
12.1 Ripple Measurement
Measure ripple with an oscilloscope using a 10× probe with the ground spring (not the alligator clip, which adds 50–100 nH of loop inductance and picks up switching noise). Set the scope to AC coupling, 20 MHz bandwidth limit, and 2 mV/div. Measure directly across the module’s VDD and GND pins.
Expected results:
- LDO-powered: < 500 μV (below scope noise floor with 10× probe; use a 1× probe or spectrum analyzer)
- Buck-powered: 1–5 mV at switching frequency, with 2–3 harmonics visible
- During TX burst: 10–30 mV transient sag for 20–50 μs, recovering within 100 μs
12.2 Inrush Measurement
Use a current probe (Hall effect, 100 MHz bandwidth) or a small sense resistor (1 Ω) with a differential probe. Trigger on the supply voltage crossing 0.5 V. Measure peak current, duration, and total charge (integrate current over time).
Pass criteria for CR2032 designs:
- Peak current < 15 mA (CR2032 max pulse)
- Duration < 10 ms (NTC thermal limit)
- VDD sag < 300 mV below nominal (avoid BOD trigger)
- Total charge < 10 μC per power-on event
12.3 Power Profiling
Use a source measure unit (SMU) or Nordic Power Profiler Kit II (PPK2) to profile the current consumption over a complete BLE connection event. Key measurements:
| Event | Duration | Current | Charge (μC) |
|---|---|---|---|
| Sleep (before event) | — | 1.5 μA | — |
| RC oscillator startup | 200 μs | 1.0 mA | 0.2 |
| Crystal oscillator startup | 300 μs | 0.8 mA | 0.24 |
| PLL lock | 150 μs | 2.5 mA | 0.375 |
| TX (0 dBm, 1 byte) | 4 μs | 5.7 mA | 0.023 |
| RX (waiting for ack) | 150 μs | 5.5 mA | 0.825 |
| Shutdown/sleep | — | 1.5 μA | — |
| Total per event | 654 μs | — | 1.66 μC |
At a 1-second interval, the average current is 1.66 μA / 1 s + 1.5 μA = 3.16 μA. With a 220 mAh CR2032 at 3.0 V, the lifetime is 220 mAh / 0.00316 mA = 69,620 hours ≈ 7.95 years. This is the theoretical maximum; real-world life is 5–7 years after accounting for self-discharge, BOD current, and sensor power.
13. Common Design Pitfalls
- Using a high-I_q LDO: The AP2112 / RT9013 / ME6211 family has 40–55 μA quiescent current. For a CR2032 design, this alone consumes the battery in 167 days. Always check I_q before designing in an LDO.
- Insufficient decoupling on VDD_PA: A single 100 nF on VDD is not enough. The PA needs its own 100 nF + 1 μF pair within 2 mm of the VDD_PA pin.
- Ignoring DC bias derating on MLCCs: A 10 μF 0805 X5R at 6.3 V loses 40% capacitance at 3.0 V DC bias. Design with the derated value, not the nominal.
- Unshielded inductor near antenna: A 2.2 μH unshielded inductor 5 mm from a chip antenna can reduce range by 3–5 dB due to magnetic field coupling. Use shielded inductors or increase spacing to >10 mm.
- BOD threshold too low: Setting BOD at 1.7 V to maximize battery life risks flash corruption below 1.8 V. Set BOD 100 mV above the minimum flash write voltage.
- No soft-start on battery insertion: 47 μF of bulk capacitance on a CR2032 causes 2–5 A inrush, collapsing the battery voltage below BOD. Add a soft-start LDO or load switch.
- Sharing VDD and VDD_PA decoupling: A single capacitor serving both pins allows PA noise to couple into the digital logic, causing timing jitter and potential flash errors.
- Long traces to decoupling caps: 5 mm of trace adds 3 nH inductance, creating a 45 Ω impedance at 2.4 GHz that nullifies the capacitor. Keep traces under 2 mm.
14. Design Checklist
- [ ] LDO quiescent current < 1 μA (for battery-powered designs)
- [ ] LDO dropout voltage < 100 mV at worst-case load and V_battery_EOL
- [ ] Buck converter switching frequency 2–4 MHz (avoids BLE band harmonics)
- [ ] Inductor: shielded, DCR < 100 mΩ, saturation > 500 mA
- [ ] Output ripple < 2 mV at module VDD (measured with 10× probe, ground spring)
- [ ] Inrush current < 15 mA peak (CR2032) or < 100 mA (USB)
- [ ] Soft-start time 1–5 ms (battery) or 0.5–2 ms (USB)
- [ ] BOD threshold ≥ min flash write voltage + 100 mV
- [ ] Tier 1 decoupling: 100 nF X7R within 2 mm of each VDD pin
- [ ] Tier 2 decoupling: 1 μF X5R within 5 mm of VDD pin
- [ ] Tier 3 bulk: 10 μF X5R near regulator output
- [ ] DC bias derating applied to all MLCC capacitance values
- [ ] VDD_PA has dedicated decoupling (not shared with VDD)
- [ ] Thermal: P_diss × θ_JA < 50 °C at maximum ambient temperature
- [ ] Power profiling: average current matches datasheet within 20%
- [ ] VDD sag during TX < 300 mV (measured at module pins, not regulator output)
15. Conclusion
Power supply design for Bluetooth module integration is a systems engineering problem that touches every aspect of module performance — RF sensitivity, battery life, thermal management, and regulatory compliance. The key takeaways: choose the right topology based on battery chemistry (LDO for CR2032, buck for Li-ion, buck-boost for alkaline); design the ripple budget from battery to PA with explicit attenuation calculations; manage inrush current with soft-start circuitry sized to the battery’s pulse capability; and verify every design decision with oscilloscope measurements and power profiling. The difference between a 2-year battery life and a 7-year battery life is often not the module choice, but the 25 μA LDO versus the 55 μA LDO on the BOM.