Every Bluetooth module lives or dies by its clock. The RF synthesizer needs a 32 MHz reference to hit the 2.4 GHz ISM band. The sleep timer needs a 32.768 kHz reference to wake up for the next advertising or connection event. If either clock drifts too far, the module misses its slot, drops the connection, or wastes power correcting itself. Yet crystal selection is often treated as an afterthought—a part copied from the reference design without understanding why those values matter.
This article breaks down crystal and clock design for Bluetooth module applications: what the BLE specification actually requires, how to calculate load capacitance correctly, how temperature and aging shift your frequency, and how to lay out the crystal on your PCB to keep it stable. We will use real numbers from nRF52832, nRF52840, and CC2640R2 datasheets so you can verify every calculation.
## 1. BLE Frequency Accuracy Requirements
The Bluetooth Core Specification (v5.4, Vol 6, Part A, Section 3.1) requires the carrier frequency to be within ±75 kHz of the channel center frequency. At 2.44 GHz (Channel 19), that is:
| Parameter | Value |
|---|---|
| Carrier frequency | 2440 MHz |
| Required accuracy | ±75 kHz |
| In ppm | ±30.7 ppm |
| BLE spec margin | ±75 kHz absolute |
However, the ±75 kHz budget includes both initial frequency error (crystal tolerance + calibration error) and drift over time (temperature + aging). Most module designs target ±20 ppm total to leave margin for the BLE receiver’s frequency estimation error, which consumes another 10–15 ppm of the budget.
### 1.1 Where Does the 75 kHz Come From?
The BLE receiver uses a frequency estimation algorithm that can correct for a portion of the frequency offset between transmitter and receiver. But if the offset exceeds the estimation range, the packet is lost. The 75 kHz limit ensures that two devices with opposite-sign offsets (one +37.5 kHz, the other −37.5 kHz) still see a net offset within the receiver’s correction capability.
### 1.2 Practical Budget Allocation
For a module designed to operate from −20°C to +60°C:
| Error Source | Typical Value | Notes |
|---|---|---|
| Crystal tolerance (initial) | ±10 ppm | Manufacturer spec at 25°C |
| Temperature stability | ±10 ppm | Over −20 to +60°C |
| Load capacitor mismatch | ±2 ppm | 1% tolerance caps |
| Aging (1 year) | ±3 ppm | First year worst case |
| PCB parasitic variation | ±2 ppm | Trace length, solder mask |
| Total | ±27 ppm | Within BLE margin |
This leaves ~4 ppm of headroom below the 30.7 ppm practical limit—tight but achievable with careful component selection.
## 2. The 32 MHz High-Frequency Crystal
The HF crystal (typically 32 MHz) serves as the reference for the PLL that generates the 2.4 GHz RF carrier. Most BLE SoCs use this crystal directly for the radio synthesizer.
### 2.1 Key Crystal Parameters
| Parameter | Symbol | nRF52832 Req | CC2640R2 Req | Typical Value |
|---|---|---|---|---|
| Nominal frequency | f0 | 32 MHz | 24 MHz | — |
| Load capacitance | CL | 12 pF | 9 pF | 8–16 pF |
| Maximum ESR | R1 | 100 ohm | 60 ohm | 30–80 ohm |
| Frequency tolerance | — | ±10 ppm | ±10 ppm | ±10–30 ppm |
| Temperature stability | — | ±10 ppm | ±10 ppm | ±10–30 ppm |
| Drive level | DL | 100 uW max | 100 uW max | 1–100 uW |
| Shunt capacitance | C0 | — | — | 1–3 pF |
### 2.2 Why nRF52832 Uses 32 MHz and CC2640R2 Uses 24 MHz
The crystal frequency must be an integer multiple (or sub-multiple) of the RF channel spacing. BLE channels are spaced 2 MHz apart. The nRF52832 PLL multiplies 32 MHz by 76.25 to reach 2440 MHz (Channel 0). The CC2640R2 uses a 24 MHz reference with a fractional-N PLL. Both approaches work; the choice is driven by the SoC architecture.
### 2.3 ESR and Oscillator Startup
The Equivalent Series Resistance (ESR) determines how hard the oscillator circuit must drive the crystal. A higher ESR means:
– Longer startup time (more time to reach stable oscillation)
– Higher startup current
– Risk of oscillation failure at temperature extremes
For the nRF52832, the internal oscillator transconductance is 200 uA/V minimum. The crystal ESR must satisfy:
gm >= 5 * 2*pi*f0 * (C0 + CL) * R1 * 2With f0 = 32 MHz, C0 = 2 pF, CL = 12 pF, R1 = 100 ohm:
gm_required = 5 * 2*pi*32e6 * (2e-12 + 12e-12) * 100 * 2
= 5 * 201061929 * 14e-12 * 200
= 5 * 201061929 * 2.8e-9
= 5 * 0.000563
= 0.002815 A/V = 2.815 mA/V
Since the nRF52832 provides 200 uA/V = 0.2 mA/V… wait, that does not meet the requirement. Let me recalculate. The Barkhausen criterion for the Pierce oscillator used in these SoCs is:
gm >= 4 * (2*pi*f0)^2 * (C0 + CL) * CL * R1With the same values:
gm_required = 4 * (2*pi*32e6)^2 * (2e-12 + 12e-12) * 12e-12 * 100
= 4 * (2.01e8)^2 * 14e-12 * 12e-12 * 100
= 4 * 4.04e16 * 14e-12 * 12e-12 * 100
= 4 * 4.04e16 * 1.68e-21 * 100
= 4 * 6.79e-3 * 100
= 4 * 0.679
= 2.716 mA/V = 2716 uA/V
Hmm, that still exceeds the 200 uA/V figure. The confusion is that the nRF52832 datasheet specifies the oscillator transconductance differently. In practice, the nRF52832 HFXO is specified to work with crystals up to 100 ohm ESR at CL = 12 pF, and the transconductance is actually much higher than 200 uA/V in the startup phase. The safe approach: follow the SoC manufacturer’s crystal specification list rather than deriving from first principles.
### 2.4 Startup Time Impact on Power
The HF crystal typically takes 200–500 us to start up and stabilize. During this time, the SoC draws its highest current (the oscillator is in maximum-drive mode). For a module advertising at 100 ms intervals:
| Phase | Duration | Current | Energy per event |
|---|---|---|---|
| Sleep | 99.2 ms | 1.8 uA | 0.178 nWh |
| HFXO startup | 400 us | 5.5 mA | 0.611 nWh |
| TX (3 channels) | 372 us | 4.8 mA | 0.496 nWh |
| HFXO shutdown | — | — | — |
| Total per adv event | — | — | 1.285 nWh |
The startup energy (0.611 nWh) is nearly 48% of the total advertising event energy. Reducing startup time (by using a lower-ESR crystal or lower CL) directly reduces average current. A crystal with ESR = 40 ohm instead of 100 ohm can cut startup time by 30–40%, saving ~0.2 nWh per event. Over a year of 100 ms advertising:
Events per year = 365.25 * 24 * 3600 / 0.1 = 315,576,000
Energy saved = 0.2 nWh * 315,576,000 = 63.1 mWh
CR2032 capacity = 220 mAh * 3V = 660 mWh
Percentage saved = 63.1 / 660 = 9.6%
A lower-ESR crystal can extend battery life by nearly 10%.
## 3. Load Capacitance Calculation
This is the most common source of frequency error in module designs. The crystal’s load capacitance (CL) is specified by the crystal manufacturer. The external capacitors must be selected to match this value after accounting for PCB parasitics.
### 3.1 The Formula
CL = (C1 * C2) / (C1 + C2) + CstrayWhere:
– C1, C2 = external load capacitor values (typically equal)
– Cstray = parasitic capacitance from PCB traces, solder pads, and SoC pins
If C1 = C2 = Cx, then:
CL = Cx/2 + Cstray
Cx = 2 * (CL - Cstray)
### 3.2 Estimating Cstray
Cstray is the trickiest part. It includes:
| Source | Typical Range |
|---|---|
| PCB trace (5 mm, 4 mil width) | 0.5–1.0 pF |
| Solder pad capacitance | 0.3–0.5 pF per pad |
| SoC pin capacitance | 2–4 pF per pin |
| Via capacitance | 0.3–0.5 pF per via |
| Total Cstray | 3–6 pF |
For the nRF52832, the datasheet specifies pin capacitance of approximately 3 pF per crystal pin. With a typical PCB layout, Cstray is about 4–5 pF total.
### 3.3 Worked Example
Target: CL = 12 pF (crystal spec), Cstray = 4.5 pF
Cx = 2 * (12 - 4.5) = 2 * 7.5 = 15 pFUsing standard E12 values: 15 pF (exact match) or 16 pF (closest standard).
If we naively used Cx = 24 pF (2 * 12, ignoring Cstray):
CL_actual = 24/2 + 4.5 = 16.5 pF
Error = (16.5 - 12) / 12 = 37.5% over
The frequency shift from load capacitance mismatch is approximately:
df/f0 = -C1_motor / (2 * (C0 + CL_actual) * (C0 + CL_spec)) * (CL_actual - CL_spec)Simplified for small deviations:
df/f0 ≈ -(CL_actual - CL_spec) / (2 * (C0 + CL_spec))With C0 = 2 pF, CL_spec = 12 pF:
df/f0 ≈ -(16.5 - 12) / (2 * (2 + 12)) = -4.5 / 28 = -0.161 = -161 ppmA 4.5 pF error in CL produces a 161 ppm frequency shift—more than 5x the BLE tolerance. The crystal would oscillate 161 ppm below its nominal frequency, causing connection failures.
### 3.4 Capacitor Tolerance Impact
Using 5% tolerance capacitors instead of 1%:
| CL Target | Cx (1%) | Cx (5%) | CL range (1%) | CL range (5%) | ppm variation (1%) | ppm variation (5%) |
|---|---|---|---|---|---|---|
| 12 pF | 15 pF | 15 pF | 11.85–12.15 | 11.55–12.45 | ±5.4 ppm | ±16.1 ppm |
With 5% caps, the load capacitance alone can cause ±16 ppm variation—consuming most of the error budget. Use 1% tolerance C0G/NP0 capacitors for crystal load caps.
## 4. The 32.768 kHz Low-Frequency Crystal
The LF crystal drives the RTC (Real-Time Counter) that controls sleep timing—when to wake up for the next advertising event or connection interval. Its accuracy determines how precisely the module hits its scheduled wake-up time.
### 4.1 Why It Matters
When a BLE module sleeps between advertising events, it sets a timer for the next wake-up (e.g., 100 ms). If the LF clock is slow by 100 ppm, the module wakes up 10 us late. The radio then has to wait for the advertising channel to be available, wasting energy.
In a connection, the master tells the slave to wake up every connection interval (e.g., 30 ms). The slave must be ready ±2 us of the anchor point. If the LF clock drifts, the slave wakes up early and listens longer, or wakes up late and misses the packet.
### 4.2 RC Oscillator vs Crystal
Many BLE SoCs offer an internal RC oscillator as an alternative to an external 32.768 kHz crystal:
| Parameter | External Crystal | Internal RC (nRF52832) | Internal RC (CC2640R2) |
|---|---|---|---|
| Accuracy (uncalibrated) | ±20 ppm | ±500 ppm | ±200 ppm |
| Calibration needed | No | Yes (every 4–8 s) | Yes (every 8 s) |
| Current consumption | 0.1–0.3 uA | 0.2 uA (running) | 0.13 uA (running) |
| Calibration current | — | ~1 uA burst | ~1 uA burst |
| BOM cost | $0.03–0.08 | $0 | $0 |
| PCB area | ~2 mm^2 | 0 | 0 |
| Startup time | 300–1000 ms | <1 ms | <1 ms |
The RC oscillator saves BOM cost and PCB area but requires periodic calibration against the HF crystal. During calibration, the HF crystal must be running, which costs energy. For modules that advertise frequently (e.g., 20 ms interval), the calibration overhead can exceed the crystal’s power consumption.
### 4.3 RC Calibration Energy Calculation
nRF52832 calibrates the RC oscillator every 4 seconds (default). Each calibration takes ~17 ms with the HF crystal running:
Energy per calibration = 5.5 mA * 3V * 17ms = 0.281 uWh
Energy per day = (86400 / 4) * 0.281 = 21600 * 0.281 = 6.07 mWh/day
External crystal energy per day:
Energy per day = 0.2 uA * 3V * 86400s = 0.052 mWh/dayThe RC oscillator’s calibration overhead is 117x the crystal’s continuous consumption. For battery-powered tags with CR2032 (660 mWh), using an external LF crystal saves ~6 mWh/day, extending life by:
660 mWh / 6 mWh/day = 110 days additional lifeAlways use an external 32.768 kHz crystal for battery-powered BLE modules.
### 4.4 LF Crystal Selection
| Parameter | Typical Value | Notes |
|---|---|---|
| Frequency | 32.768 kHz | Tuning fork type |
| Load capacitance | 7–12.5 pF | Lower CL = smaller caps |
| ESR | 30–70 kohm | Must check SoC spec |
| Tolerance | ±20 ppm | Common; ±10 ppm available |
| Temperature | −10/+20 ppm | Tuning fork parabolic curve |
| Package | 3215 (3.2×1.5mm) or 2012 (2.0×1.2mm) | SMD |
The tuning fork crystal has a parabolic temperature characteristic centered at 25°C:
df/f0 = k * (T - 25)^2Where k ≈ −0.035 ppm/°C². At −10°C or +60°C:
df/f0 = -0.035 * (60 - 25)^2 = -0.035 * 1225 = -42.9 ppmThis is a significant drift. If the module operates at temperature extremes, the LF clock can drift by 40+ ppm, causing timing errors in connection events.
## 5. Temperature Effects and Compensation
### 5.1 HF Crystal Temperature Characteristics
AT-cut crystals (used for 32 MHz) have a cubic temperature characteristic:
df/f0 = a1*(T-25) + a3*(T-25)^3 + a5*(T-25)^5The exact coefficients depend on the crystal cut angle. For a typical AT-cut crystal specified as ±10 ppm over −20 to +60°C, the curve has inflection points near 25°C and may peak at ±8 ppm around +85°C.
### 5.2 Software Temperature Compensation
Some BLE SoCs (e.g., nRF52840) include an internal temperature sensor that can be used to compensate crystal frequency drift. The approach:
1. Read the die temperature from the internal sensor
2. Look up the expected frequency offset from a pre-calibrated table
3. Apply a correction to the radio frequency register
For the nRF52840, the frequency correction register (FREQ) has 1 MHz resolution steps. The fine-tuning is done via the SFD timeout adjustment and frequency estimation in the radio peripheral. In practice, software compensation can reduce the total frequency error from ±25 ppm to ±10 ppm over the full temperature range.
### 5.3 TCXO as an Alternative
A Temperature-Compensated Crystal Oscillator (TCXO) integrates a temperature sensor and compensation circuit inside the oscillator package. Typical specs:
| Parameter | Standard Crystal | TCXO |
|---|---|---|
| Accuracy over temp | ±10–30 ppm | ±0.5–2 ppm |
| Current consumption | 0 (passive) | 0.3–1.5 mA |
| BOM cost | $0.05 | $0.30–0.80 |
| Start-up time | 200–500 us | 1–5 ms |
| Package size | 3.2×2.5mm | 2.5×2.0mm or smaller |
For most BLE module applications, the standard crystal with careful CL calculation provides sufficient accuracy. TCXO is justified only when:
– Operating across extreme temperature ranges (−40 to +105°C)
– Requiring long connection intervals (>1 second) where accumulated drift is large
– Supporting BLE Audio (LE Audio) which has tighter timing requirements
## 6. PCB Layout for Crystals
### 6.1 Golden Rules
1. Minimize trace length: Keep crystal-to-SoC traces under 3 mm. Every mm adds ~0.1 pF of parasitic capacitance.
2. Symmetric layout: Route both crystal pins with equal-length traces. Asymmetry causes unequal parasitic capacitance, shifting the oscillation frequency.
3. Ground guard ring: Surround the crystal with a ground copper pour on the same layer, connected to the SoC ground via multiple vias.
4. No signals under the crystal: Route no high-speed or switching signals beneath the crystal pads on any layer.
5. Load caps close to crystal: Place C1 and C2 as close to the crystal pads as possible, with short ground returns.
6. Separate ground return: The crystal ground should connect directly to the SoC ground pad, not through a shared plane with noisy peripherals.
### 6.2 Layout Parasitic Capacitance Estimation
A typical 4-layer PCB stackup (signal-ground-power-signal) with 4 mil trace width:
| Element | Capacitance |
|---|---|
| 3 mm trace (signal to ground plane) | 0.3 pF |
| Solder pad (0.6×0.3 mm) | 0.2 pF |
| Via (signal to ground) | 0.3 pF |
| SoC pin (internal) | 3.0 pF |
| Total per pin | 3.8 pF |
| Total Cstray (both pins) | 7.6 pF |
If your layout has longer traces (e.g., 6 mm), Cstray increases to ~5 pF per pin (10 pF total). This changes the required external capacitor:
Cx = 2 * (12 - 10) = 4 pFA 4 pF capacitor is at the edge of practical availability. This is why short crystal traces are critical—if Cstray is too large, you cannot achieve the target CL with standard capacitor values.
### 6.3 Ground Guard Ring Layout
GND ----+----------+---- GND
| |
| [XTAL] |
| / \ |
C1 C2
+--+--+--+-+
| |
GND GND
(vias)
The guard ring should be at least 0.5 mm wide, connected to the SoC ground pad with at least 2 vias, and completely encircle the crystal and load capacitors. The ring prevents noise from adjacent signals from coupling into the crystal oscillator.
## 7. Clock Tree Design in BLE Modules
### 7.1 Clock Sources in a Typical BLE SoC
| Clock | Frequency | Source | Used For |
|---|---|---|---|
| HFXO | 32 MHz | External crystal | RF synthesizer, high-speed peripherals |
| HFXO (alt) | 32 MHz | External TCXO | Same, with better accuracy |
| HFINT | 32 MHz | Internal RC | Fast startup, not accurate enough for RF |
| LFXO | 32.768 kHz | External crystal | RTC, sleep timing |
| LFINT | 32.768 kHz | Internal RC | RTC (with calibration) |
| LFCLK (synth) | 32.768 kHz | Derived from HFXO | RTC (high accuracy, high power) |
### 7.2 Clock Gating for Power Savings
Modern BLE SoCs implement automatic clock gating: when a peripheral is idle, its clock is disabled. The module firmware can further reduce power by:
– Disabling unused peripherals in the PRCN (Power and Clock Management) registers
– Using the LF clock for all timing when the radio is off
– Starting the HFXO only when needed (just before radio events)
– Using PPI (Programmable Peripheral Interoperability) to start/stop clocks without CPU intervention
For the nRF52832, the typical clock state machine during advertising:
Sleep: LFCLK running (LFXO), HFXO off, CPU off
→ RTC compare event triggers PPI
→ PPI starts HFXO (400 us startup)
→ HFXO ready event triggers RADIO
→ TX on 3 advertising channels (376 us)
→ RADIO END event triggers PPI
→ PPI stops HFXO
→ CPU goes back to sleep
This entire sequence happens without CPU intervention, minimizing power. The key is that the LFCLK accuracy determines how close to the scheduled time the RTC fires. If the LFCLK drifts, the HFXO may start too early (wasting power) or too late (missing the window).
### 7.3 Crystal Startup Time Optimization
The HFXO startup time depends on:
– Crystal ESR (lower = faster)
– Load capacitance (lower = faster)
– Oscillator drive strength (higher = faster, but risk of over-driving)
– Negative resistance margin (larger margin = faster)
For the nRF52832 with a 32 MHz, CL=12 pF, ESR=40 ohm crystal:
| Drive Setting | Startup Time | Current During Startup |
|---|---|---|
| Default | 350 us | 5.5 mA |
| Boost (enabled) | 180 us | 8.2 mA |
| Normal (boost off) | 420 us | 4.1 mA |
The boost mode trades higher startup current for shorter startup time. The optimal choice depends on the advertising interval:
Energy_default = 5.5mA * 350us = 1.925 uC
Energy_boost = 8.2mA * 180us = 1.476 uC
Boost mode actually saves 23% energy per startup event while also reducing the time to first packet. Enable HFXO boost mode for advertising intervals < 200 ms.
## 8. Measurement and Validation
### 8.1 Frequency Error Measurement
The most direct method is to use a BLE tester (e.g., Nordic nRF52 DK + nRF Connect, or Rhode & Schwarz CBT) to measure the carrier frequency offset:
1. Put the module in continuous TX mode (unmodulated carrier) on a specific channel
2. Measure the carrier frequency with a spectrum analyzer or frequency counter
3. Calculate the offset: df = f_measured – f_channel_center
4. Convert to ppm: error = df / f_channel_center * 1e6
| Channel | f_center | Expected f_measured (0 ppm) |
|---|---|---|
| 0 | 2402 MHz | 2402.000000 MHz |
| 19 | 2440 MHz | 2440.000000 MHz |
| 39 | 2480 MHz | 2480.000000 MHz |
A module with a well-tuned crystal should show < 20 ppm error across all three channels. If the error is consistent across channels (e.g., all +35 ppm), the crystal is off-frequency—likely a load capacitance issue. If the error varies significantly between channels, the PLL or reference clock multiplier may have an issue.
### 8.2 Temperature Chamber Testing
To verify temperature stability:
1. Place the module in a temperature chamber
2. Set the chamber to −20°C, 0°C, 25°C, 40°C, 60°C, 80°C
3. At each temperature, measure the carrier frequency (after 15 min soak)
4. Plot frequency error vs temperature
A typical result for an AT-cut ±10 ppm crystal:
| Temperature | Frequency Error (ppm) |
|---|---|
| −20°C | −8.2 |
| 0°C | +3.1 |
| 25°C | +0.5 |
| 40°C | +5.8 |
| 60°C | +7.2 |
| 80°C | +4.1 |
The cubic curve is visible: the error dips at −20°C, peaks around +60°C, then starts returning. If any point exceeds ±20 ppm, investigate the load capacitance or consider a tighter-tolerance crystal.
### 8.3 Production Testing Approach
In mass production, every module should be frequency-tested:
1. Quick test (< 2 seconds): Module transmits a single advertising packet on Channel 19. A test fixture measures the carrier frequency. Pass/fail threshold: ±30 ppm.
2. Calibration: If the frequency error is within ±50 ppm but outside ±30 ppm, apply a software correction (trim the load capacitor value register if the SoC supports internal capacitor trimming, or flag the module for capacitor rework).
3. Yield expectation: With 1% load capacitors and a verified PCB layout, > 99% of modules should pass on the first test.
The nRF52832 supports internal load capacitor trimming (CAPACITANCE register, 0–15 pF range, 0.5 pF steps). This allows software calibration of the crystal frequency without changing physical components:
If error > +20 ppm: decrease internal capacitance by 0.5 pF steps
If error < -20 ppm: increase internal capacitance by 0.5 pF steps
Each 0.5 pF change shifts the frequency by approximately 7–8 ppm (depends on C0 and CL). With 31 steps (0–15 pF), the trim range is ±110 ppm—sufficient to correct for any crystal/load cap variation.
## 9. Common Design Pitfalls
### 9.1 Copying Reference Design Blindly
SoC reference designs are optimized for a specific crystal on a specific PCB stackup. If your PCB has different layer spacing, dielectric constant, or trace geometry, the parasitic capacitance will differ, and the load caps will be wrong. Always measure and verify the frequency on your actual PCB.
### 9.2 Ignoring Cstray
Setting C1 = C2 = 2*CL (e.g., 24 pF for CL = 12 pF) is the most common error. This ignores Cstray entirely and results in 40–160 ppm frequency error. Always calculate Cstray from your PCB layout and adjust the external cap values accordingly.
### 9.3 Using X7R Load Capacitors
X7R capacitors have a voltage coefficient that causes capacitance to vary by 10–15% with applied voltage. Since the crystal oscillator applies near-zero DC voltage, this is less of an issue, but X7R also has higher temperature variation (±15% vs ±30 ppm for C0G). Always use C0G/NP0 dielectric for crystal load capacitors.
### 9.4 Crystal Over-Driving
If the oscillator drive strength is too high, the crystal dissipates more power than its rated drive level (typically 100 uW max). This causes:
– Frequency shift (the crystal frequency depends on drive level)
– Premature aging (the crystal frequency drifts faster)
– Physical damage in extreme cases (cracked quartz element)
The nRF52832 allows configuring the HFXO drive strength. If the crystal ESR is low (e.g., 30 ohm), reduce the drive strength to avoid over-driving. Check that the crystal dissipated power is within spec:
P_crystal = I_rms^2 * R1Where I_rms is the AC current through the crystal, measurable with a current probe or calculable from the oscillation voltage swing across C1.
### 9.5 LF Crystal Startup Time
The 32.768 kHz crystal has a notoriously long startup time—up to 1 second. If the module firmware initializes the RTC immediately after power-on and the crystal has not stabilized, the first few timing intervals will be inaccurate. Always wait for the LFXO-ready event before entering sleep mode, or use the internal RC oscillator for the first few seconds after boot.
### 9.6 Vias in Crystal Traces
Placing vias on the crystal trace increases parasitic inductance and capacitance, degrading oscillator performance. Route crystal traces entirely on the top layer with no vias between the crystal pads and the SoC pins.
## 10. SoC Comparison: Crystal Requirements
| Parameter | nRF52832 | nRF52840 | CC2640R2F | TLSR8253 |
|---|---|---|---|---|
| HF freq | 32 MHz | 32 MHz | 24 MHz | 24 MHz |
| HF CL (typical) | 12 pF | 12 pF | 9 pF | 12 pF |
| HF max ESR | 100 ohm | 100 ohm | 60 ohm | 80 ohm |
| HF startup time | 350–500 us | 350–500 us | 200–400 us | 300–500 us |
| LF support | LFXO + RC | LFXO + RC | LFXO + RC | LFXO + RC |
| LF CL (typical) | 12 pF | 12 pF | 12.5 pF | 12.5 pF |
| Internal cap trim | Yes (0.5 pF steps) | Yes (0.5 pF steps) | No | No |
| HFXO boost mode | Yes | Yes | No | No |
| TCXO support | Via external pin | Via external pin | No | No |
The nRF52 series has the most flexible crystal support, including internal capacitance trimming and boost mode. The CC2640R2 has tighter ESR requirements (60 ohm max) but faster startup. The TLSR8253 is the most restrictive—no internal trimming means you must get the physical load caps right.
## 11. Design Checklist
Before finalizing your module design, verify each item:
– [ ] Crystal tolerance + stability + aging < ±25 ppm total
– [ ] Load capacitance calculated with measured Cstray from PCB layout
– [ ] Load capacitors are C0G/NP0, 1% tolerance
– [ ] Crystal traces < 3 mm, symmetric, no vias
– [ ] Ground guard ring around crystal and load caps
– [ ] No high-speed signals routed under or near crystal
– [ ] ESR within SoC specification with adequate margin (> 2x)
– [ ] HFXO startup time measured and within power budget
– [ ] LF crystal (not RC oscillator) for battery-powered applications
– [ ] LF crystal startup time accounted for in boot sequence
– [ ] Frequency error measured on actual PCB at room temperature
– [ ] Temperature chamber test passed over operating range
– [ ] Production test fixture ready for frequency verification
– [ ] Internal cap trimming register configured (if supported)
– [ ] HFXO boost mode enabled for advertising intervals < 200 ms
## 12. Summary
Crystal and clock design is the foundation of BLE module performance. A 2 pF error in load capacitance can cause a 50+ ppm frequency shift—enough to fail BLE compliance and drop connections. The key takeaways:
1. Calculate Cstray from your actual PCB layout, not from the reference design. A 4-layer PCB with 3 mm traces typically has 3.8–5 pF per pin of parasitic capacitance.
2. Use C0G/NP0 1% capacitors for crystal load caps. X7R and 5% tolerance parts consume too much of the frequency error budget.
3. Always use an external 32.768 kHz crystal for battery-powered modules. The RC oscillator’s calibration overhead costs 100x more energy than the crystal itself.
4. Minimize crystal startup time by selecting low-ESR crystals and enabling boost mode. Startup energy accounts for 40–50% of advertising event energy.
5. Verify on real hardware: measure frequency error at room temperature and in a temperature chamber. Use internal cap trimming for production calibration if available.
6. Follow the SoC manufacturer’s crystal specification for ESR, CL, and drive level. These are validated through extensive characterization and should not be second-guessed.
For modules designed to operate across industrial temperature ranges (−40 to +85°C), consider a TCXO for the HF clock or implement software temperature compensation using the SoC’s internal temperature sensor. The additional 0.3–1.5 mA current consumption is justified when standard crystals cannot maintain ±20 ppm accuracy across the full range.
When selecting a Bluetooth module for your application, verify that the module manufacturer has done this crystal design work for you—testing frequency accuracy across temperature, validating load capacitance on the production PCB, and providing a frequency error specification in the datasheet. A well-designed module should specify ±20 ppm or better over the operating temperature range, with production-tested frequency accuracy on every unit.
